I’m old enough to remember that a 386 not respecting R/W page bits in ring 0 was a big deal that had to be worked around in SW, incurring performance penalty. Fast forward a couple of decades and it seems paging is still a difficult subject. Make no mistake, this is no bug (Intel admits as much) but a design decision that produced perhaps faster but ultimately unsecure CPUs. Welp, not my problem, I have a buggy Ryzen 🙂
Anyway, I have some GDEMUs for sale so I will be taking orders this Saturday. Not all that many so it’ll probably be a short sale. More devices are in production and I should have some more Saturn ODEs soon as well. As in maybe this month but I’m not sure about that yet.
Very sorry about lack of PCE status updates, my December was more busy than I predicted, but there will be something worth showing in the coming weeks. Turns out working on so many projects at once can slow things down quite a lot. Who knew?
EDIT: GDEMU orders are
open closed. Before you complain about this being sneaky, trust me, it’s the better solution. A lot of you claim you’d be willing to get on the list even if it meant months of waiting, so long you were sure you are getting one. Let’s just say I tried that and know from experience it’s BS so I won’t be doing it this way anymore.